Reliable and large-scale distributed storage is the backbone of high-performance computing, big data analytics, and many other pervasive applications. The continued scaling of distributed storage requires failure recovery schemes that have short latency and low penalty on the network bandwidth. This demand is answered by locally recoverable erasure (LRC) codes and minimum storage regenerating (MSR) codes. Hyper-speed data-centric computing and analysis need data access speed in the next higher order. On the other hand, coding schemes with low redundancy and good correction capability are necessary to tackle the deteriorating reliability of the storage media caused by technology scaling. One of the most promising candidates to address this issue is the generalized integrated interleaved (GII) codes, which are also a type of LRC codes.
This talk presents algorithmic reformulations and architectural modifications for reducing the implementation complexity of these coding schemes for hyper-speed large-scale distributed storage. GII codes and one category of high-performance LRC and MSR codes are built by nesting/coupling Reed-Solomon codes, which are defined over finite fields. I will show that by exploiting various constructions of finite fields and subfield elements, the nesting/coupling complexity can be greatly reduced and the constraints on the code parameters can be relaxed. We also developed algorithmic and architectural modifications to eliminate the clock frequency bottleneck and reduce the silicon area requirement of the decoders. These recent results will also be discussed in this talk.
Xinmiao Zhang received her Ph.D. degree in Electrical Engineering from the University of Minnesota, Twin Cities. She was a Timothy E. and Allison L. Schroeder Assistant Professor 2005-2010 and Associate Professor 2010-2013 at Case Western Reserve University. She has been with Western Digital/SanDisk 2013-2017, and joined The Ohio State University in 2017 as an Associate Professor. She also held visiting positions at the University of Washington, Seattle, 2011-2013 and Qualcomm in 2008. Dr. Zhang’s research spans the areas of VLSI architecture design, digital storage and communications, security, and signal processing.
Dr. Zhang received an NSF CAREER Award in January 2009. She is also the recipient of the Best Paper Award at 2004 ACM Great Lakes Symposium on VLSI and 2016 International SanDisk Technology Conference. Dr. Zhang is elected to serve on the Board of Governors of the IEEE Circuits and Systems Society for the 2019-2021 term and as a Vice-Chair of the Data Storage Technical Committee (DSTC) of the IEEE Communications Society 2017-2020. She is also serving on the IEEE CASCOM, VSA, and DISPS technical committees. She has been a chair or member of the technical program and organization committees of many conferences, including ISCAS, ICC, SiPS, GLOBECOM, GLSVLSI, and NVMW. She has been an associate editor for the IEEE Transactions on Circuits and Systems-I since 2010, and was a recipient of the Best Associate Editor Award in 2013.